1. Field of the Invention
The present invention relates to a stack-type semicon ductor device in which a plurality of semiconductor elements are stacked, and to a method of manufacturing the same.
2. Description of the Related Art
In order to realize downsizing, higher-density packaging and the like of a semiconductor device, a stack-type multichip package in which a plurality of semiconductor elements are stacked and sealed in one package has been in practical use in recent years. In the stack-type multichip package, the plural semiconductor elements are stacked in sequence on a circuit board via an adhesive film. Electrode pads of the semiconductor elements are electrically connected to electrode parts of the circuit board via bonding wires. Such a stacked structure is packaged by sealing resin, whereby the stack-type multichip package is formed.
In a memory device utilizing NAND type flash memories, for example, a plurality of memory chips are stacked on a lead frame and sealed so as to develop the memory capacity of the memory device. In such a stack-type memory device as described above, the bonding wires to connect the top layer semiconductor chip electrode and the lead frame are inevitably too long. As a result, the bonding wires are flowed at the wire bonding process and/or the resin sealing process so that the adjacent bonding wires with the respective different electric potentials may be contacted with one another and short-circuited. In this point of view, the reliability of the stack-type memory device can not be enhanced. Moreover, the wire bonding design becomes difficult and the design allowable range is restricted so that the stack-type memory device can not be commercially available.
In view of the problem as described above, in such a semiconductor device as a NAND-type flash memory or the like, such a semiconductor chip structure is proposed as connecting the electrode pads with the same electric potential as one another of the semiconductor chips and the lead frame with bonding wires (refer to Patent Publications No. 1 and 2). In the semiconductor chip structure, the electrode pads of the top semiconductor chip are bonded to the electrode pads of the lower semiconductor chip with bonding wires. Stud bumps are formed at the corresponding electrode pads of the lower semiconductor chip in advance. Then, the electrode pads of the lower semiconductor chip are bonded to the lead frame with bonding wires. In this way, the electrode pads of the semiconductor chips with the same electric potential as one another can be bonded to the lead frame via the lower semiconductor chip(s).
With such a conventional semiconductor chip structure as described above, however, at least twice bonding steps are required for the electrode pads of the semiconductor chips via the bonding wires. In this case, since supersonic vibration is applied to the electrode pads of the semiconductor chips at the wire bonding process, the bonding wires may be deformed and the electric connection between the electrode pads of the semiconductor chips may be failed, resulting in the lower productive yield of the stack-type semiconductor device. Moreover, the bonding number of times for the electrode pads of the semiconductor chips is increased at the wire bonding process so that the manufacturing steps is increased and the productive efficiency is lowered.                [Patent Document 1] JP-A 11-135714        [Patent Document 2] JP-A 2003-243442        